The present invention relates to a non-volatile memory array, and more particularly to a flash memory array with self-limiting erase to prevent over-erasing.
The fabrication of flash memories or electrically erasable programmable read only memories (EEPROMs) utilizing metal oxide semiconductor (MOS) technology is well known in the prior art. These EEPROMs employ memory cells utilizing floating gates which are generally formed from polysilicon and which are completely surrounded by an insulator. Electrical charge is transferred to and removed from the floating gate to control the threshold voltage of one or more MOS transistors in a memory cell. A floating gate is "programmed" when a charge is stored on it. The cell is "unprogrammed" or "erased" when the floating gate is discharged.
A problem with the single transistor flash cell or single-transistor EEPROM cell is over-erasure. An overerasing condition occurs when, as a result of erase, the floating gate potential is sufficiently high during a read operation that an unselected cell conducts current, thereby providing an erroneous reading. A proposed solution to the over-erasing problem is to add an additional transistor to each cell to block output of erroneous data resulting from the over-erased floating gate. This two-transistor cell then forms each EEPROM memory cell.
However, there are drawbacks to this proposed solution. One such drawback is that EEPROM memory cells require sophisticated manufacturing processes. Increasing their complexity increases their cost of manufacture. Another drawback is that EEPROM memory cells requiring two transistors per cell require more surface area on a silicon wafer than is required by a single transistor cell, thereby decreasing the number of cells that can De obtained for a predetermined area which also increases cost.
One approach to simplifying the EEPROM memory cell has been to use a split-gate memory cell that is essentially the EEPROM memory cell combined into a hybrid two transistor design that requires less area on a silicon wafer. The manufacturing process for the split-gate transistor is less sophisticated than that for the EEPROM memory cell, but is still more sophisticated than that for a single transistor memory cell. Furthermore, the split-gate cell also requires more area than a single transistor cell.
U.S. Pat. No. 5,357,466, issued Oct. 18, 1994 to the present inventor, assigned to United Microelectronics Corporation, discloses a flash memory cell with a self-limiting erase to prevent the floating gate from being over-erased. The subject matter of that patent is hereby incorporated by reference as if fully set forth herein.
The memory cell of the '466 patent comprises first and second MOS transistors. The first and second transistors have a common source, first and second separate drains, a common floating gate and a common control gate. The first transistor has a higher threshold voltage than the second transistor. A feedback path is provided between the drain of the second transistor and the common control gate to limit the discharge to prevent over-erasing. This flash memory cell, however, requires more silicon wafer area than a single transistor cell.
U.S. Pat. No. 5,241,507, issued Aug. 31, 1993 to Vincent Fong, also incorporated herein by reference as if fully set forth herein, discloses a single-transistor flash memory array employing prevention circuitry for minimizing the effect of any floating gates in an over-erased state when accessing data stored in the memory array device. The prevention circuit includes a column line coupling a current limiting device in each row together in a common column. The memory array device also employs a row current limiting device which couples a row of flash cells to the erase potential. The second row switching is activated to prevent a false signal generated by an over-erased flash cell in the same column as a selected flash cell is being accessed for data from masking the data retrieval from the desired flash cell. As a result of employing the prevention circuit, the flash memory array can employ single transistor floating gate memory cells which are susceptible to being over-erased during erase operation. Thus, despite the necessity of adding five transistors for every two rows of memory cells, the overall density of the memory array is enormously increased over memory arrays of the prior art which required two transistors per memory cell. This patented method, however, still cannot prevent the floating gates from being over-erased.
Therefore, what is needed is a non-volatile memory array employing single-transistor memory cells that does not exhibit the over-erasing problem.